Many types of integrated circuit packaging techniques are currently used to increase the yield and efficiency in making highly cost effective electronic components. One such packaging technique that is commonly used is referred to as chip scale packaging. Chip scale packaging involves cutting individual chips from a silicon wafer after the chip has been processed to form an integrated circuit. Each chip is then individually placed one at a time in a package. The package provides mechanical and environmental protection for the chip and enables electrical connections to be made from the chip to other electronic components. In a chip scale package, the chip and the package are substantially the same size with the package typically 0% to 15% larger than the chip by area.
Another process used to package an integrated circuit chip is known as wafer level packaging. Wafer level packaging involves forming the package on the chip before it is cut from the silicon wafer. This process reduces the time needed to package a chip because an entire silicon wafer of chips can be packaged at once prior to cutting the individual chips from the silicon wafer. Thus, a wafer level packaging process reduces the time needed to individually package each chip making it much less costly than chip scale packaging.
FIG. 1 illustrates a silicon wafer 100 comprised of like integrated circuit chips 101, 101′, 101″ and so forth such that the surface of the silicon wafer 100 is as densely populated with integrated circuit chips as possible. Each integrated circuit chip contains input/output (I/O) pads 102 that enable electrical connection to and from the chip to other devices that are not part of either the chip 101 or the silicon wafer 100. The input output pads 102 must be contained within the surface area of the IC for which they are associated. For ICs with many input/output pads, the pitch or distance 103 between pads can be small and not compatible with the electrical connection capability of other devices such as resistors, capacitors, or printed circuit boards.
Prior art FIG. 2A illustrates a flow chart diagram describing the processes upon which the chip scale package addresses the input/output compatibility with other devices. The flow chart 200 defines the process flow for a chip scale package. The process includes fabricating the IC chips on a silicon wafer 251. The silicon wafer is then cut 253 into individual IC chips and placed onto an interposer substrate 255. An interposer substrate is typically fabricated in 8-up strips using commonly known PCB processes 257. Wire is then bonded from the IC input/output pad to the interposer I/O pad 259. An epoxy mold compound is then overmolded on the IC interposer 261 and the IC and package are then singulated from the strip 263.
FIG. 2B illustrates a prior art diagram of the cross-section the device 201 where an integrated circuit chip 202 uses a wire 203 bonded to the chip. A substrate 204 is used to make electrical connection to interposer substrate 205. The interposer substrate 205 is larger than the chip 202 and redistributes the pitch of the integrated circuit input output pads to a larger pitch that is compatible with electrical connection requirements of resistors, capacitors, or printed circuit boards.
Similarly, prior art FIGS. 3A and 3B illustrate how a wafer level package addresses the input/output compatibility with other devices. Specifically, FIG. 3A is a prior art flow chart 300 that defines the process flow for a wafer level package. This process begins where the IC chips are fabricated on a silicon wafer 351. The silicon wafer is then coated with epoxy dielectric 353 and vias are formed in the epoxy dielectric to expose the IC input/output pad 355. Next, the vias are metalized 357 and the metal input/output pads are formed on the silicon wafer using vias to connect to the IC input/output pads 359. Finally, the IC and package are singulated from the wafer 361.
FIG. 3B illustrates a top view of the device silicon wafer 303. The process as defined in FIG. 3A produces input/output pads 301 compatible with resistors, capacitors, and printed circuit boards. In order to obtain compatible input/output pads 301, the integrated circuits 302, 302′, and 302″ on silicon wafer 303 are spaced at a distance or pitch 304 such that pitch 304 is greater than pitch 103. The increased pitch 304 requires more silicon area for integrated circuit 302 on silicon wafer 303 than for the same integrated circuit 101 on silicon wafer 100.
Thus, those skilled in the art will recognize that the number of integrated circuits processed on a given silicon wafer will be less for a wafer level package because of the extra space required for the input/output pad pitch. This reduces the overall processing cost since fewer steps are required to make a wafer level packaged integrated circuit as compared with a chip scale packaged IC. Hence, cost saving with few processing steps is negated by the increase in cost associated with the decrease in the total number of ICs processed on the silicon wafer.
In light of the shortcomings of the prior art, the need exists to provide an integrated circuit package processing technique that will yield a substantially high density of integrated circuit chips on the silicon substrate and still provide reduced processing steps for making input/output connections to each individual chip and package.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.